Hardware Modeling in VHDL for Mixed Hardware/Software System Level Co-simulation of Embedded Systems

We present a method for modeling and then simulating a mixed hardware/software embedded system implementation in VHDL starting from a high level design representation. In our approach, a complete system description including the communication interfaces is generated automatically in VHDL: Software is modeled by using behavioral VHDL constructs, annotated with timing information derived from basic block-level timing estimates, while hardware can be either pre-existing Intellectual Property (IP) or synthesized from a functional speci cation. Our approach has been incorporated into a comprehensive co-design environment, and while we describe elsewhere in detail the software synthesis and modeling in VHDL[9, 8], we focus here on the Finite State Machine with Datapath (FSMD) Register Transfer Level (RTL) modeling of hardware, and the subsequent system validation in VHDL.